As electrically writable/erasable nonvolatile semiconductor memory devices, an EEPROM (Electrical Erasable and Programmable Read Only Memory) and a flash memory has been currently used. Each memory cell in the nonvolatile semiconductor memory devices represented by the EEPROM and the flash memory has a charge storage region represented by a conductive floating gate electrode or a trapping insulating film surrounded by an oxide film under the gate electrode of a MIS (Metal Insulator Semiconductor) transistor, and charges are stored in the charge storage region as stored information and are read as the threshold voltage of the MIS transistor.
Examples of the memory cell having the trapping insulating film as the charge storage region include MONOS-type memory cells (hereinafter, simply referred to as MONOS memory cells). Among them, split-gate memory cells each having two gate electrodes of a memory gate electrode and a selection gate electrode have been widely used in recent years. The split-gate memory cell uses a trapping insulating film as a charge storage region, and is therefore capable of discretely storing charges therein and excellent in data retention reliability. In addition, because of the excellent data retention reliability, oxide films formed above and below the trapping insulating film can be thinned to provide the advantage of allowing reductions in the voltages for write/erase operations or the like. Also, the use of the split-gate memory cell allows hot electrons to be injected into the trapping insulating film by a SSI (Source Side Injection) method having high injection efficiency, and high-speed and low-current writing can be achieved. Moreover, because of easy control of write and erase operations, the advantage is also provided that a peripheral circuit can be scaled down. The trapping insulating film refers to an insulating film which enables charge storage. As an example of the trapping insulating film, a silicon nitride film can be shown.
Examples of a cell structure of the split-gate memory cell include that shown in FIG. 26, in which, after a selection gate electrode 6 is formed first, an ONO (Oxide Nitride Oxide) film including a lower oxide film 24, a silicon nitride film 25 and an upper oxide film 26 is formed, and a memory gate electrode 12 is formed in the shape of a sidewall spacer of the selection gate electrode 6 (see, for example, Japanese Unexamined Patent Application Publication 2005-123518 (Patent Document 1)).
An advantage of the split-gate memory cell is that, since the ONO film is present between the memory gate electrode 12 and the selection gate electrode 6, breakdown voltage is easily and reliably provided between the memory gate electrode 12 and the selection gate electrode 6, and the distance therebetween can be reduced to be almost as short as the thickness of the ONO film. When the distance between the memory gate electrode 12 and the selection gate electrode 6 can be reduced, the gap resistance of a channel portion under a region between the memory gate electrode 12 and the selection gate electrode 6 decreases, and a large read current can be obtained. Note that the reference numerals 1, 3, 16s and 16d in FIG. 26 denote a semiconductor substrate, a p-well, a source region and a drain region, respectively.
Patent Document 2 (Japanese Unexamined Patent Application Publication No. 2009-54707) discloses a technology which forms a bird's beak in an insulating film between a selection gate and a semiconductor substrate to increase the thickness of the insulating film at the end portion of the selection gate in the gate length direction thereof, thereby increasing a disturb life through the relaxation of an electric field.